Oracle CPU-56T Bedienungsanleitung

SPARC/CPU−56TReference GuideP/N 224548 Revision AANovember 2004

10 SPARC/CPU−56TProduct Error Report

OpenBoot Firmware Diagnostics100 SPARC/CPU−56TThe system responds by incrementing a number every second. Press any key to stop thetest.NetworkTo monit

Displaying System Information OpenBoot FirmwareSPARC/CPU−56T 101Displaying System InformationThe Forth Monitor provides several commands to display sy

OpenBoot Firmware Displaying System Information102 SPARC/CPU−56TTable 19: Commands to Display System InformationCommandDescriptionbanner Displays syst

Resetting the System OpenBoot FirmwareSPARC/CPU−56T 103Resetting the SystemIf your system needs to be reset, there are two possibilities:S Software re

OpenBoot Firmware Activating OpenBoot Help104 SPARC/CPU−56TActivating OpenBoot HelpThe Forth Monitor contains an online help which can be activated by

Activating OpenBoot Help OpenBoot FirmwareSPARC/CPU−56T 105l@ ( addr −− n ) place on the stack the 32−bit data at location addraw@ ( addr −− n ) place

106 SPARC/CPU−56T6Maps and RegistersInterrupt Map 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SPARC/CPU−56T 107Interrupt Enable Control Register 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maps and Registers Interrupt Map108 SPARC/CPU−56TInterrupt MapThe following table lists all interrupt sources, their vectors from the UIC to the PIE,

Interrupt Map Maps and RegistersSPARC/CPU−56T 109Interrupt Source PriorityOffsetCPU InternalVectorRIC VectorPMC4 D 09167D71617161PS/2 keyboard 2B167E9

SPARC/CPU−56T 11TablesIntroductionTablei1aaaaaaaStandard Compliances 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maps and Registers Physical Memory Map110 SPARC/CPU−56TPhysical Memory MapThe UltraSPARC−IIi+ has a 41−bit wide physical address range. This address r

Physical Memory Map Maps and RegistersSPARC/CPU−56T 111Physical Address Range PA<41..0> DIMM TypeMemory LocationBankSize001.0000.000016aa − 001.

Maps and Registers Physical Memory Map112 SPARC/CPU−56TThe PCI device PCIO, part of the UltraSPARC−IIi+ chip set, must be available at power upfor boo

Physical Memory Map Maps and RegistersSPARC/CPU−56T 113Address Range in PA<40:0> DescriptionEBus CS#Size1FF.F010.000016a − 1FF.F0FF.FFFF1615 MBy

Maps and Registers System Configuration Registers114 SPARC/CPU−56TSystem Configuration RegistersThe CPU board implements a set of system configuration

System Configuration Registers Maps and RegistersSPARC/CPU−56T 115Address Range inPA<40:0>DescriptionDefaultAccessSize1FF.F160.0148161 Byte r/w

Maps and Registers System Configuration Registers116 SPARC/CPU−56TAddress: 1FF.F160.010016Table 26: Miscellaneous Control RegisterBitName Description

System Configuration Registers Maps and RegistersSPARC/CPU−56T 117Bit AccessDefaultDescriptionName6 ETH3 EN Status of Ethernet interface 30: Disableda

Maps and Registers System Configuration Registers118 SPARC/CPU−56TLED Control Register 2This register is used to switch between the different operatio

System Configuration Registers Maps and RegistersSPARC/CPU−56T 119Address: 1FF.F160.011216Table 29: LED Control Register 3Bit Name Description Default

12 SPARC/CPU−56TTablei29aaaaaaLED Control Register 3 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maps and Registers System Configuration Registers120 SPARC/CPU−56TAddress: 1FF.F160.011316Table 30: LED Control Register 4BitName Description Default

System Configuration Registers Maps and RegistersSPARC/CPU−56T 121Bit AccessDefaultDescriptionName5..3 0 Reserved 0002r6 STAT ACFAIL This bit reflects

Maps and Registers System Configuration Registers122 SPARC/CPU−56TAddress: 1FF.F160.013016Table 32: Watchdog Timer Control RegisterBitName Description

System Configuration Registers Maps and RegistersSPARC/CPU−56T 123Watchdog Timer Status RegisterThe Watchdog Timer Status register reflects the watchd

Maps and Registers System Configuration Registers124 SPARC/CPU−56TAddress: 1FF.F160.014016Table 35: Timer Control RegisterBit Name Description Default

System Configuration Registers Maps and RegistersSPARC/CPU−56T 125Address: 1FF.F160.014416Table 37: Timer Status RegisterBit Name Description Default

Maps and Registers System Configuration Registers126 SPARC/CPU−56TAddress: 1FF.F160.014816 − 1FF.F160.014B16Table 38: Timer Initial Control RegistersB

System Configuration Registers Maps and RegistersSPARC/CPU−56T 127Address: 1FF.F160.014C16 − 1FF.F160.014F16Table 39: Timer Counter Status RegisterBit

Maps and Registers System Configuration Registers128 SPARC/CPU−56TAddress: 1FF.F160.018016Table 40: Interrupt Enable Control RegisterBitName Descripti

System Configuration Registers Maps and RegistersSPARC/CPU−56T 129Bit AccessDefaultDescriptionName2 IP_TEMP Reflects if a temperature interrupt is pen

SPARC/CPU−56T 13FiguresIntroductionFigurei1aaaaaaaFunction Blocks 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maps and Registers System Configuration Registers130 SPARC/CPU−56TBit AccessDefaultDescriptionName2 RST WD Reflects whether the last reset has been ge

System Configuration Registers Maps and RegistersSPARC/CPU−56T 131Bit AccessDefaultSwitch Setting/FunctionalityName3 SW1−4 Reset/Abort key enabling0:

Maps and Registers System Configuration Registers132 SPARC/CPU−56TBit AccessDefaultSwitch Setting/FunctionalityName5 .. 4 SW4−2 and SW4−1 VME Slot 1 D

System Configuration Registers Maps and RegistersSPARC/CPU−56T 133Bit AccessDefaultDescriptionName5 PMC3/4 VIO This bit is set to 1 if the PMC modules

Maps and Registers System Configuration Registers134 SPARC/CPU−56TAddress: 1FF.F160.01EF16Table 47: Hardware Revision RegisterBit Name Description Acc

System Configuration Registers Maps and RegistersSPARC/CPU−56T 135Address: 1FF.F160.01FF16Table 49: I2C 2 RegisterBit Name Description Defaulta Access

136 SPARC/CPU−56TATroubleshooting

Error List TroubleshootingSPARC/CPU−56T 137Error ListA typical VMEbus system is highly sophisticated. This chapter can be taken as an errorlist for de

Troubleshooting Error List138 SPARC/CPU−56TProblem SolutionPossible ReasonBoard does not boot Wrong boot devicea Check the OpenBootproperty boot−devic

SPARC/CPU−56T 139BBattery Exchange

14 SPARC/CPU−56TUsing this GuideThis Reference Guide is intended for users qualified in electronics or electricalengineering. Users must have a workin

Battery Exchange Battery Exchange140 SPARC/CPU−56TBattery ExchangeThe battery provides data retention of seven years summing up all periods of actual

Battery Exchange Battery ExchangeSPARC/CPU−56T 1414. Install battery in such a way that the dot marked on top of battery covers dotmarked on chip.a5.

142 SPARC/CPU−56TIndexAAborting the board 59. . . . . . . . . . . . . . . . . . . . . . Bbanner 101. . . . . . . . . . . . . . . . . . . . . . . . . .

SPARC/CPU−56T 143I2C Devices 82. . . . . . . . . . . . . . . . . . . . . . . . . . . LLED stati 58. . . . . . . . . . . . . . . . . . . . . . . . . .

144 SPARC/CPU−56Twatch−net 98. . . . . . . . . . . . . . . . . . . . . . . . . . . .

SPARC/CPU−56T 145Product Error ReportProduct: Serial No.:Date Of Purchase: Originator:Company: Point Of Contact:Tel.: Ext.:Address:___________________

SPARC/CPU−56T 15Notation DescriptionPossibly dangerous situation: slight injuries to people orPossibly dangerous situation: slight injuries to people

16 SPARC/CPU−56TAbbreviation DescriptionFFAEFField Application EngineersFIFO First In First OutFPGA Field−Programmable Gate ArrayIIBMUIIntelligent Boa

SPARC/CPU−56T 17Abbreviation DescriptionPCIO Peripheral Component Interconnect Input/OutputPHY Physical LayerPIE PCI Interrupt EnginePLCC Plastic Lead

18 SPARC/CPU−56TOrder No. DescriptionDateRev.223146 AA April 2004 Corrected numberof SUN patch foraudio support.Now it reads109896−17; addednote to ab

SPARC/CPU−56T 19Other Sources of InformationFor further information refer to:Company www. DocumentALI Corporation ali.com.tw ALI M1535D+ Southbridge d

2 SPARC/CPU−56TCopyrightThe information in this publication is subject to change without notice. Force Computers, GmbH reserves the right to makechang

20 SPARC/CPU−56TSafety NotesThe text in this chapter is a translation of the Sicherheitshinweise" chapterThis section provides safety precaution

SPARC/CPU−56T 21Setting/resetting the switches during operation causes board damage. Therefore, checkand change switch settings before you install the

22 SPARC/CPU−56TCheck the total power consumption of all components installed (see the technicalspecification of the respective components). Ensure th

SPARC/CPU−56T 23SicherheitshinweiseDieser Abschnitt enthält Sicherheitshinweise, die bei Einbau, Betrieb und Wartung desBoards zu beachten sind.Wir si

24 SPARC/CPU−56Tgekennzeichneten Schalter nicht, da diese Schalter mit produktionsrelevantenFunktionen belegt sein können, die im normalen Betrieb Stö

SPARC/CPU−56T 25entstehen können. Stellen Sie vor dem Einschalten des Stroms sicher, dass sich aufdem Board kein Kondensat befindet und betreiben Sie

26 SPARC/CPU−56TS Verwenden Sie die Batterien länger als sieben Jahre, kann dies zu Datenverlustenführen. Tauschen Sie deshalb die Batterie aus, bevor

SPARC/CPU−56T 271IntroductionFeatures 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction Features28 SPARC/CPU−56TFeaturesThe SPARC/CPU56 is a high−performance VME single−board computer based on the 650Mhz UltraSPARC IIi+ proce

Features IntroductionSPARC/CPU−56T 29Figure 1: Function Blocks

SPARC/CPU−56T 3World Wide Web: www.fci.com24−hour access to on−line manuals, driver updates, and applicationnotes is provided via SMART, our Solutions

Introduction Standard Compliances30 SPARC/CPU−56TStandard CompliancesThe CPU board was designed to comply with the standards listed below.Table 1: Sta

Ordering Information IntroductionSPARC/CPU−56T 31Ordering InformationWhen ordering board variants, hard− and software upgrades use the order numbersgi

Introduction Ordering Information32 SPARC/CPU−56TOrder No. DescriptionAccessory120456 SPARC/IOBP−IO−56/3 Three−row variant of I/O board′sIOBP111332 AC

SPARC/CPU−56T 332InstallationAction Plan 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34 SPARC/CPU−56TFRCflash 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Action Plan InstallationSPARC/CPU−56T 35Action PlanIn order to install the board, the following steps are necessary and will be described infurther de

Installation Requirements36 SPARC/CPU−56TRequirementsIn order to meet the environmental requirements, the CPU board has to be tested in thesystem in w

Requirements InstallationSPARC/CPU−56T 37Feature Non−OperatingOperatingShock 5g/11 ms halfsine 15g/11 ms halfsineFree fall 100 mm / 3 axes 1,200 mm /

Installation Hardware Accessories38 SPARC/CPU−56THardware AccessoriesThe following upgrades and accessories are available:S IOBPs for CPU and I/O Boa

Hardware Accessories InstallationSPARC/CPU−56T 39Note:aOn the IOBP−CPU−56−3 the RS−232 signals are limited to RXD, TXD, RTS andCTS.aOn the IOBP−CPU−5

4 SPARC/CPU−56T

Installation Hardware Accessories40 SPARC/CPU−56TPMC#4 PMC#3 PMC#2PMC slot 2 supports a 64−bit data bus width with a maximum frequency of 33 MHz andi

Hardware Accessories InstallationSPARC/CPU−56T 41Installation ProcedureNote:aS To ensure proper EMC shielding, either operate each PMC slot with a bl

Installation Hardware Accessories42 SPARC/CPU−56T2. Carefully remove I/O board from CPU board by unplugging it from PMCconnectorsFinishChanging Signa

Hardware Accessories InstallationSPARC/CPU−56T 434. Fix voltage key to I/O board by fastening screwVoltage KeyScrewFinishInstalling the PMC ModuleSta

Installation Hardware Accessories44 SPARC/CPU−56T4. Fasten screwsFinishReinstalling I/O BoardStart1. Plug I/O board onto PMC connectors of CPU board2

Hardware Accessories InstallationSPARC/CPU−56T 45The actual memory module installation procedure is described in theaSPARC/MEM−550Installation Guidea

Installation Switch Settings46 SPARC/CPU−56TSwitch SettingsBoard DamageSetting/resetting the switches during operation causes board damage.Therefore,

Switch Settings InstallationSPARC/CPU−56T 47Switch DescriptionNo.2 Enable termination for SCSI 2OFF (default): Termination enabledON: Termination disa

Installation Board Installation48 SPARC/CPU−56TBoard InstallationBoard DamageInstalling the board into a powered system may damage this and other boar

Board Installation InstallationSPARC/CPU−56T 49Installing the CPU BoardProcedureStart1. Check system documentation for all important steps to be taken

SPARC/CPU−56T 5ContentsUsing this GuideOther Sources of InformationSafety NotesSicherheitshinweise1 IntroductionFeatures 28. . . . . . . . . . . . . .

Installation Board Installation50 SPARC/CPU−56T4. Remove interface cables, if applicable5. Unfasten screwsa6. Remove boardFinishPowering UpWe recommen

Board Installation InstallationSPARC/CPU−56T 51Installing SolarisThe CPU board is designed to run with Solaris 8 2/02 or higher with the 64−bit kernel

Installation Board Installation52 SPARC/CPU−56TFor audio I/O and IDE ATA 100 support, you have to install Solaris patches. Thefollowing table provides

Board Installation InstallationSPARC/CPU−56T 53Further information on these drivers is given in the following sections.aFRCgeiThe assignment of the dr

Installation Board Installation54 SPARC/CPU−56TS Slave windowsS InterruptsS DMA controllerS VME arbiterS MailboxesAdditionally, the FRCvme package pro

Board Installation InstallationSPARC/CPU−56T 55S Enables and triggers watchdog functionsTo enable the watchdog, set switch SW1−3 to ONS Increases the

56 SPARC/CPU−56T3Controls, Indicators, and ConnectorsFront Panel 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Front Panel Controls, Indicators, and ConnectorsSPARC/CPU−56T 57Front PanelThe following figure shows the connectors, keys and LEDs available on the f

Controls, Indicators, and Connectors Front Panel58 SPARC/CPU−56TLEDsAll four LEDs available at the front panel are multi−purpose LEDs. Depending on th

Front Panel Controls, Indicators, and ConnectorsSPARC/CPU−56T 59LED Description3 VME Bus Activity (default)Red: Universe II asserted VME SYSFAIL signa

6 SPARC/CPU−56TRS−422 Cable 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controls, Indicators, and Connectors Front Panel60 SPARC/CPU−56TS Keyboard/MouseS EthernetS SCSISerial I/OTwo serial RS−232 interfaces A and B are ava

Front Panel Controls, Indicators, and ConnectorsSPARC/CPU−56T 61135246123465Mouse DataGNDMouse Clockn.c.Vccn.c.Figure 9: PS/2 Mouse Connector PinoutEt

Controls, Indicators, and Connectors Front Panel62 SPARC/CPU−56T12345678910111213141516171819202122232425262728293031323334SCSIx_D12+SCSIx_D13+SCSIx_D

On−Board Connectors Controls, Indicators, and ConnectorsSPARC/CPU−56T 63On−Board ConnectorsThe following connectors are on−board:S PMCS Memory moduleS

Controls, Indicators, and Connectors On−Board Connectors64 SPARC/CPU−56TPMC#3163642Pn24It carries user I/O signals that are routed to the I/O board′ s

On−Board Connectors Controls, Indicators, and ConnectorsSPARC/CPU−56T 65P8P9Figure 15: Location of Memory Module ConnectorsIDEThe CPU board provides o

Controls, Indicators, and Connectors On−Board Connectors66 SPARC/CPU−56T2468101214161820222426283032343638404244GNDIDE1_D8IDE1_D9IDE1_D10IDE1_D11IDE1_

On−Board Connectors Controls, Indicators, and ConnectorsSPARC/CPU−56T 67P2 carries the following Force Computers specific signals:aS 10/100Mbit Ethern

Controls, Indicators, and Connectors On−Board Connectors68 SPARC/CPU−56TFigure 19: CPU Board P2 VMEbus Connector Pinout Rows C + DI/O BoardP1 carries

On−Board Connectors Controls, Indicators, and ConnectorsSPARC/CPU−56T 69Figure 20: I/O Board P2 VMEbus Connector Pinout Rows Z – B

SPARC/CPU−56T 74 Devices’ Features and Data PathsBlock Diagram 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controls, Indicators, and Connectors On−Board Connectors70 SPARC/CPU−56TFigure 21: I/O Board P2 VMEbus Connector Pinout Rows C + D

SPARC/CPU−56T 714Devices’ Features and Data PathsBlock Diagram 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

72 SPARC/CPU−56TReal−Time Clock and NVRAM 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block Diagram Devices’ Features and Data PathsSPARC/CPU−56T 73Block DiagramFigure 22: CPU Board Block Diagram

Devices’ Features and Data Paths Block Diagram74 SPARC/CPU−56TFigure 23: I/O Board Block Diagram

UltraSPARC IIi+ Processor Devices’ Features and Data PathsSPARC/CPU−56T 75UltraSPARC IIi+ ProcessorThe UltraSPARC IIi+ processor is based on the SPARC

Devices’ Features and Data Paths Interrupt Controller76 SPARC/CPU−56TInterrupt ControllerThe UltraSPARC−IIi+ provides a 6−bit wide interrupt vector fo

PCI Bus A Devices’ Features and Data PathsSPARC/CPU−56T 77PCI Bus APCI bus A is the primary PCI bus. It runs at 33 MHz and is 32 bit wide. The followi

Devices’ Features and Data Paths PCI Bus A78 SPARC/CPU−56TS Integral FIFOs for write posting to maximize bandwidth utilizationS Programmable DMA contr

PCI Bus B Devices’ Features and Data PathsSPARC/CPU−56T 79PCI Bus BPCI bus B runs at 33 MHz and is 64 bit wide. It is the secondary PCI bus of the CPU

8 SPARC/CPU−56TCORE Workflow 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Devices’ Features and Data Paths PCI Bus B80 SPARC/CPU−56TMedia Independent InterfaceTwo on−board Intel LXT971 PHY devices are connected to the MII. T

EBus Devices’ Features and Data PathsSPARC/CPU−56T 81EBusThe EBus is a generic slave 8−bit wide Direct Memory Access (DMA) bus (pseudo ISAbus) to whic

Devices’ Features and Data Paths EBus82 SPARC/CPU−56Tinterrupt is generated is set to 1.25s. Once the watchdog timer is running, it is onlypossible to

EBus Devices’ Features and Data PathsSPARC/CPU−56T 83Ethernet Interface 1/3 SwitchingAs mentioned earlier in this guide, Ethernet interface 1 is avail

Devices’ Features and Data Paths EBus84 SPARC/CPU−56TReset Source DescriptionPower−up reset If one or more on−board voltages are not withintheir thres

EBus Devices’ Features and Data PathsSPARC/CPU−56T 85The device offers the following features:S Four independent full−duplex serial channelsS Four ind

Devices’ Features and Data Paths PCI Bus C86 SPARC/CPU−56TPCI Bus CPCI Bus C has the following devices attached to it:S SENTINEL64 PCI−To−PCI bridgeS

SPARC/CPU−56T 875OpenBoot FirmwareIntroduction 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OpenBoot Firmware Introduction88 SPARC/CPU−56TIntroductionThe OpenBoot firmware consists of the Common Operations and Reset Environment(CORE), the pow

Introduction OpenBoot FirmwareSPARC/CPU−56T 89Additionally, CORE is designed to reach the following goals:S Ability to use I/O devices including seria

SPARC/CPU−56T 9UltraSPARC−IIi+ Internal CSR Space 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OpenBoot Firmware Introduction90 SPARC/CPU−56TCORE CommandsIn order to change or interrupt the boot process in CORE, the following commands can beexec

Introduction OpenBoot FirmwareSPARC/CPU−56T 91boot <device−specifier> <filename> <−bootoption>Optional Boot ParametersTable 13: Boot

OpenBoot Firmware Introduction92 SPARC/CPU−56TAlias SCSI InterfaceSCSI Deviceadiskc Disk SCSI−target−ID c 1diskb Disk SCSI−target−ID b 1diska Disk SCS

Introduction OpenBoot FirmwareSPARC/CPU−56T 93Alias SCSI InterfaceSCSI Deviceadisk24 Disk SCSI−target−ID 4 2disk23 Disk SCSI−target−ID 3 2disk22 Disk

OpenBoot Firmware Introduction94 SPARC/CPU−56TAlias Devicettyb Serial interface Btyyc Serial interface Ctyyd Serial interface DvmeVMEOBDIAGOBDIAG stan

Introduction OpenBoot FirmwareSPARC/CPU−56T 95When OBDIAG is called, the <obdiag> test prompt appears and you can now choose therequired test. Y

OpenBoot Firmware Introduction96 SPARC/CPU−56Tobdiag>asetenv diag−verbosity 2aadiag−verbosity =aaaaaa2aaHit any key to return to the main menua<

NVRAM Boot Parameters OpenBoot FirmwareSPARC/CPU−56T 97NVRAM Boot ParametersThe OpenBoot firmware holds its configuration parameters in NVRAM. To see

OpenBoot Firmware Diagnostics98 SPARC/CPU−56TDiagnosticsThe Forth Monitor includes several diagnostic routines. These on−board tests let youcheck devi

Diagnostics OpenBoot FirmwareSPARC/CPU−56T 99probe−scsi−allThe actual response depends on the devices on the SCSI buses.Note:aA terminal message as an